Spin-Orbit Torque MRAM: Fundamentals, Technology Integration and Perspectives
Kévin Garello, Imec
(Currently at SPINTEC)
October 2, 2020
Microelectronics industry is facing major challenges related to the volatility of cache memory elements (usually SRAM and eDRAM). Indeed, due to decreasing devices size, leakage current in standby mode are now dominating the power dissipation, and the increased density lead to heat dissipation and reliability issues. Consequently, the introduction of non-volatility (NV) at cache level holds great promises for advance logic nodes as it would lead to improved performances and largely decrease the power consumption of microprocessors. Among NV memory technologies, magnetic random-access memory (MRAM) technology, and mostly Spin-Transfer-Torque (STT) family, has gained a lot of attention due to its scalability, low power and relatively low access times, as well as a compatibility with scaled CMOS processes and voltages. In fact, past years have seen major foundries and tool suppliers investing significant R&D resources into embedded STT-MRAM. They recently started prototyping demonstrators beyond 28 nm node with chip capacities larger than 1 Gb, progressively maturing for mass production. Despite all these advantages, STT-MRAM also faces several challenges: i. the write process is still relatively inefficient and long compared to SRAM, ii. speed gain requires to increase current flowing through the bit cell – the magnetic tunnel junction (MTJ) –, which imposes a severe stress and leads to a reduced endurance of the MTJ and increased error rates. Today, this mostly limits the use of STT-MRAM for slow SRAMs and eFlash replacements in caches memories.
Spin-Orbit Torque (SOT) is an alternative MRAM writing mechanism originating from the spin-orbit interaction and mediated by Spin Hall and Rashba effects. SOT distinguishes by offering the possibility to switch magnetization using in-plane currents, unlike STT that requires a current flow in the perpendicular direction through MTJ. Such new memory class, SOT-MRAM, promise to mitigate some of the above issues: it is a three terminal MTJ-based concept that allows isolating the read and the write path. It results in significant improvement of the read stability, the write speed and the endurance of the device; therefore opening the path to address SRAM replacement in lowest cache level by MRAM.
Across this presentation, I will cover a vision on the different challenges to take-up SOT-MRAM from material and stack optimization to technology large-scale integration and circuit design. After reviewing some key physics involved and material developments, I will describe a full-scale integration process of perpendicular magnetized SOT-MRAM devices on 300mm wafers, using industrial methods and CMOS compatible processes. We demonstrate state-of-the-art properties of W-based top-pinned magnetic tunnel junction (MTJ) with perpendicularly magnetic anisotropy (PMA) that possess large endurance (>1011), and that can be switched at sub-nanosecond regimes (210ps) with power as low as 300fJ on 60nm devices. Secondly, I will introduce field-free switching solutions and with a focus on our manufacturable approach that is integration friendly, and that does not compromise SOT-MTJ cells performances. Finally, I will discuss progress needs to bring SOT-MRAM toward industrial maturity and to diverse its application spectra.
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 K. Garello et al., Manufacturable 300mm platform solution for Field-Free Switching SOT-MRAM, IEEE Symposium on VLSI Circuit, 194-T195 (2019).